The innovative solutions proposed by TERABOARD consist of developing advanced intra-board and edge interfaces, with ultra-high density and scalability in bandwidth, low insertion loss and low energy consumption. The target of energy cost per channel is 2.5 pJ/bit, with a manufacturing cost of 0.1 $/Gb/s in volumes. These indicators are 10 times better with respect to the commercial state of the art.
The intra-board communication will be a novel concept based on a 3D passive interconnection platform with no intersections and no need of Wavelength Division Multiplexing (WDM). To reduce the overall power consumption of a data center, intra-rack communications will avoid the use of WDM, cutting the fibers cost and the footprint needed by fiber connectors. In both intra-board and intra-rack communications, TERABOARD will demonstrate a 10-times reduction of required power with respect to present commercial solutions.
3D passive interconnection platform: Starboard
TERABOARD will develop the following functionalities:
- A silica-based platform (called Starboard) for inter-node connections with unprecedented bandwidth densities and limitless scalability, very low insertion loss and with possibility of embedded functionalities as filters
- Intra-board transceiver banks for low power optical interconnection over short distances (40 cm), with aggregate bandwidth of 0.7 Tb/s/node (25 Gb/s x 28 waveguides), consumption of 2.5 pJ/bit and bandwidth density greater than 15 Tb/s/cm2
- Intra-rack interconnections (2 m) transceiver banks with aggregate bandwidth of 1.7 Tb/s (32 channels at 56 Gb/s) that will be split in blocks of 8-fiber arrays operating at 56 Gb/s/ each channel, with consumption of 2.5 pJ/bit and bandwidth density greater than 30 Tb/s/cm2
- Edge transceiver banks for intra-data center interconnections (2000 m), with aggregate bandwidth of 1.7 Tb/s (32 channels at 56 Gb/s) that will be arranged in 4 wavelengths Coarse Wavelength Division Multiplexing (CWDM) at 56 Gb/s, with bandwidth density of 7 Tb/s/cm2 and energy consumption of 6 pJ/bit
- A novel on-chip optical connector that transforms the small mode of the silicon photonics waveguides into a low index contrast mode, pluggable to an optical fiber array by means of a standard connector (MPO or MTP), with good alignment tolerance and low overall loss
- A novel approach for integrating lasers directly on the silicon photonics platform, combining advantages of classical flip chip integration and heterogeneous integration based on wafer bonding
- Advanced photonic integrated circuits on 300 mm SOI wafers, with 3D electronic-photonic integration, 56 Gb/s applications, 40 GHz photodiodes and low power consumption modulators to reach the 2.5 pJ/bit overall target of energy consumption
The silica based interconnection board, Starboard, between four processors and a switch ending on an edge connector